A switched-mode power converter (also referred to as a “power converter”) is an electronic power processing circuit that converts an input voltage waveform into an output voltage waveform, both typically but not necessarily dc waveforms, by periodically switching power switches coupled to an inductive circuit element. The power switches are controlled with a conduction period referred to as a “duty cycle.” The duty cycle is a ratio represented by the conduction period of a power switch to a switching period thereof. Thus, if a power switch conducts for half of the switching period, the duty cycle for the power switch would be 0.5 (or 50 percent). Feedback controllers associated with power converters manage an operation thereof by controlling the conduction periods of power switches employed therein. Generally, a feedback controller is coupled to an output of a power converter in a feedback loop configuration (also referred to as a “control loop” or “closed control loop”) to regulate an output characteristic of the power converter circuit such as an output voltage.
Typically, a feedback controller measures an output characteristic of the power converter circuit, and based thereon, modifies the duty cycle of the power switches of the power converter circuit. Additionally, as the need for systems such as a microprocessor or other load powered by the power converter dynamically change (e.g., as a computational load on the microprocessor changes), the feedback controller should be configured to dynamically increase or decrease the duty cycle of the power switches therein to maintain the output characteristic at a desired value.
FIG. 1 is a simplified schematic diagram of an exemplary step-down switching regulator circuit of the prior art. Step-down switching regulators are power converters that convert a dc input voltage to a lower dc output voltage, usually without dc isolation therebetween. While the power converter illustrated employs a non-isolated, buck, switching regulator topology, those skilled in the art should understand that other converter topologies such as an isolated forward or flyback converter topology can be employed to convert an input voltage to an output voltage, and include converters that step up or step down an output voltage to a voltage level higher or lower than the input voltage. Such converters are well known in the art and exemplary circuit drawings will not be illustrated or described in the interest of brevity.
The buck switching regulator circuit illustrated in FIG. 1 receives a dc input voltage Vin from a source of electrical power (represented in the figure by the battery 105) at an input thereof and typically provides a regulated output voltage Vout to power, for instance, a microprocessor coupled to an output of the switching regulator. In keeping with the principles of a buck converter topology, the output voltage Vout is generally less than the input voltage Vin such that a switching operation of the power converter can regulate the output voltage Vout. A main power switch Qmain (e.g., a field-effect transistor) is enabled to conduct for a primary interval (generally co-existent with a primary duty cycle “D” of the main power switch Qmn as produced by a controller, not shown) and couples the input voltage Vin to an output filter inductor Lout. During the primary interval, an inductor current ILout flowing through the output filter inductor Lout increases as a current flows from the input to the output of the power converter. An ac component of the inductor current ILout is filtered by the output capacitor Cout.
During a complementary interval (generally co-existent with a complementary duty cycle “1−D” of the main power switch Qmain, also as produced by a controller, not shown), the main power switch Qmain is transitioned to a non-conducting state and an auxiliary power switch Qaux (e.g., a freewheeling field-effect transistor or freewheeling diode) is enabled to conduct. The auxiliary power switch Qaux provides a conductive path to maintain a continuity of the inductor current ILout flowing through the output filter inductor Lout. During the complementary interval, the inductor current ILout flowing through the output filter inductor Lout decreases. In general, the duty cycle of the main and auxiliary power switches Qmain, Qaux may be adjusted by a feedback controller to maintain a regulation of the output voltage Vout of the power converter. Those skilled in the art should understand, however, that the conduction periods for the main and auxiliary power switches Qmain, Qaux may be separated by a small time interval to avoid cross conduction therebetween and beneficially to reduce the switching losses associated with the power converter.
FIG. 2A depicts waveforms of the circuit in FIG. 1 under normal operating conditions. An oscillator establishes the period of a switching cycle with a clock waveform such as the clock waveform 201. A feedback controller produces a duty-cycle controlling signal 205 with a conduction period D for the main switch Qmain. During the conduction period D, the load current 215 flowing through the main power switch Qmain, increases at a rate substantially proportional to the voltage difference between the input voltage and the output voltage. During the complementary period 1−D, the load current 225 flows through the auxiliary power switch Qaux, and decreases at a rate substantially proportional to the output voltage of the power converter. The current through the output inductor is the sum of the currents 215 and 225, and is shown as the inductor current waveform 235. The dc load current level is illustrated by the dotted lines 245 in FIG. 2A.
In practical applications of power converters, it is generally necessary to sense the output current delivered to the load or another current such as a power switch current internal to the power converter and to responsively modulate or disable the operation of the power converter if the output current or the other sensed current exceeds a design or other limiting value. A current that exceeds a design value, referred to as an overcurrent condition, can damage the power converter, load circuit elements, or even the interconnecting wiring therebetween. An overcurrent condition can be caused, for example, by an unexpected operation of the load circuit, a blown or damaged circuit component, or an improper external connection to the circuit such as a misapplication of a test instrument.
It is also generally necessary to protect against an overcurrent condition during startup of the power converter. During startup, output filter capacitors, such as the filter capacitor Cout illustrated in FIG. 1 and any additional filtering capacitors that may be coupled to the load, draw substantial current as the output voltage increases, typically from a discharged voltage level to a regulated voltage level. The current required to charge the capacitors coupled across the output terminals of the power converter is substantially proportional to the summed capacitance of the capacitors coupled across the output, and substantially inversely proportional to the length of the time interval during which the output voltage is raised to the required voltage level. Conflicting requirements in system designs that include power converters typically limit an output current to a limiting value to protect circuit components, but also require that the output voltage be brought to a regulated voltage level in as short a time interval as possible. An ideal power converter design for startup in view of these requirements would provide an output current substantially at the maximum, limiting current level.
In circuit designs for overcurrent protection in prior-art switched-mode power converters, current in a power-converter power switch is typically monitored. Monitoring schemes include monitoring power switch current when the power switch is turned on, or alternatively, current in a circuit element in the output portion of the circuit such as an output filter inductor. When an overcurrent condition is detected in the prior-art, a power switch is turned off for the remainder of the switching cycle in which the overcurrent condition was sensed.
FIG. 2B depicts waveforms of the circuit in FIG. 1 with the addition of a process to monitor the current in the main power switch and to terminate main power switch conduction, i.e., the duty cycle, when the current 215 in the main power switch exceeds an overcurrent limit 217. Waveforms in FIG. 2B that correspond to waveforms in FIG. 2A with the same reference designations will not be redescribed. When the current 215 in the main power switch exceeds an overcurrent limit, an overcurrent signal 255 is generated to terminate the duty cycle before its termination by the feedback controller, and the inductor current then declines at a rate substantially proportional to the output voltage.
An overcurrent protection arrangement such as described above can be effective to protect circuit elements for a range of operating conditions. However, particularly for cases of low output voltage during startup or for a low-impedance fault coupled across the output of the power converter, the very short power converter duty cycle required to control the overcurrent condition may result in a runaway condition for power switch current. The runaway condition is a consequence of the finite time required to turn a semiconductor switch on or off, resulting in a minimum effective duty cycle for the power switch, particularly for power converter circuits with a switching frequency exceeding 100 kHz. The runaway condition can also occur for a buck switching regulator circuit that converts a high input voltage, such as a voltage of 15 volts or more to a low output voltage such as a voltage of 3.3 volts or less, which inherently requires a short duty cycle during normal operation. In buck-type switching regulators, duty cycle is roughly the ratio of output voltage to input voltage.
FIG. 2C depicts waveforms of the circuit in FIG. 1, including an overcurrent limit 217 and an overcurrent signal 255. FIG. 2C illustrates an overcurrent condition for a low output voltage caused by a low-impedance fault coupled across the output or during startup, both of which produce a low output voltage. The duty cycle D is illustrated in FIG. 2C at a minimum value. The main power switch current increases until it reaches the overcurrent limit, which produces the overcurrent signal 255 that terminates the duty cycle. The inductor current, which flows through the auxiliary power switch during the complementary duty cycle 1−D, decreases only slightly due to the low output voltage. The clock signal eventually initiates a new switching cycle for the power converter. The main power switch current then starts at a value near the overcurrent limit, and exceeds the overcurrent limit before the following duty cycle can be terminated. In this manner, the current in the output inductor, which supplies the output current, increases from cycle to cycle, resulting in a runaway current condition for the power converter.
Another control scheme to control an overcurrent condition is described in Wilcox, et al., in U.S. Pat. No. 5,481,178. The Wilcox patent is directed toward a switching regulator circuit wherein the operation of two active power switches is intermittently disabled at low load current when a charge in an output filtering capacitor is sufficient to maintain a regulated output voltage during a power switch disabling interval. Wilcox, et al., recognize that the normal, periodic operation of a power switch in a switched-mode power converter is a process that contributes to circuit inefficiency. The control arrangement they describe, while increasing power conversion efficiency at light loads by intermittently disabling power switches when output current is low, fails to control an output current under a low-impedance fault condition (high output current) or during startup.
A further scheme in the prior art to provide overcurrent protection is operation of a power converter in a hiccup mode. A hiccup mode shuts down the switched-mode power converter for a pre-set, fixed time period when an overcurrent condition is detected. Such designs, which work over a limited range of operating conditions, carry a risk of the power converter output not reaching the required output voltage at startup because the resulting output inductor current with hiccup operation is insufficient to supply the required startup load current with this control method.
A principal limitation of the prior-art circuits is thus inability to adaptively respond to an output overcurrent condition over a range of possible fault conditions encountered during operation of the power converter circuit, particularly for low-impedance faults coupled across the output terminals of the power converter, and during power converter startup with substantial capacitance coupled across the output terminals. In addition, overcurrent protection schemes of the prior art generally are not configured for easy implementation in an integrated circuit. Furthermore, the complex relationships among system parameters including components externally added to the power distribution arrangement generally require substantial analysis before implementation of a cost-effective, flexible overcurrent protection process in an integrated circuit. A need thus exists for an improved overcurrent protection scheme that can prevent output current from exceeding a design limit for a wide range of operating conditions, can reliably provide sufficient current for startup with a range of loads, can straightforwardly be implemented with digital control logic, can adaptively provide overcurrent protection with minimal design effort, and can start up a power converter in a substantially minimal time.